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WM8281ECS/R 데이터시트(PDF) 113 Page - Cirrus Logic

부품명 WM8281ECS/R
상세설명  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R 데이터시트(HTML) 113 Page - Cirrus Logic

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WM8281
Rev 4.0
113
ASRC1R_ENA
ASRC1L_ENA
ASRC1L_SRC
ASRC1R_SRC
ASRC1 Left (90h)
ASRC1 Right (91h)
ASRC2R_ENA
ASRC2L_ENA
ASRC2L_SRC
ASRC2R_SRC
ASRC2 Left (92h)
ASRC2 Right (93h)
ASRC_RATE1
(= SAMPLE_RATE_n)
ASRC_RATE2
(= ASYNC_SAMPLE_RATE_n)
The ASRC provides asynchronous conversion between the SYSCLK and ASYNCCLK CLOCK domains.
ASRC_RATE1 identifies the SYSCLK-related sample rate (SAMPLE_RATE_n).
ASRC_RATE2 identifies the ASYNCCLK-related sample rate (ASYNC_SAMPLE_RATE_n).
Figure 40 Asynchronous Sample Rate Converters (ASRCs)
The ASRC1 and ASRC2 input control registers (see Figure 40) are located at register addresses
R2688 (A80h) through to R2712 (A98h).
The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600
through to R3000). Generic register definitions are provided in Table 8.
The *_SRCn registers select the input source(s) for the respective ASRC processing blocks. Note that
the selected input source(s) must be configured for the same sample rate as the ASRC to which they
are connected.
The bracketed numbers in Figure 40
, eg. “(90h)” indicate the corresponding *_SRCn register setting
for selection of that signal as an input to another digital core function.
The register bits associated with the ASRCs are described in Table 24.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3808
(0EE0h)
ASRC_EN
ABLE
3
ASRC2L_ENA
0
ASRC2 Left Enable
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
2
ASRC2R_ENA
0
ASRC2 Right Enable
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
1
ASRC1L_ENA
0
ASRC1 Left Enable
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled



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