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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8281ECS/R 데이터시트(PDF) 116 Page - Cirrus Logic |
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WM8281ECS/R 데이터시트(HTML) 116 Page - Cirrus Logic |
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116 / 392 page  WM8281 116 Rev 4.0 WM8281 supports 3 ISRC blocks, ie. n = 1, 2 or 3 ISRCn_INT2_ENA ISRCn_INT3_ENA ISRCn_INT4_ENA ISRCn_INT1_ENA ISRCnINT1_SRC ISRCnINT3_SRC ISRCnINT4_SRC ISRCnINT2_SRC ISRC1 INT1 (A0h) ISRC2 INT1 (A8h) ISRC3 INT1 (B0h) ISRC1 INT2 (A1h) ISRC2 INT2 (A9h) ISRC3 INT2 (B1h) ISRC1 INT3 (A2h) ISRC2 INT3 (AAh) ISRC3 INT3 (B2h) ISRC1 INT4 (A3h) ISRC2 INT4 (ABh) ISRC3 INT4 (B3h) ISRCn_DEC2_ENA ISRCn_DEC3_ENA ISRCn_DEC4_ENA ISRCn_DEC1_ENA ISRCnDEC1_SRC ISRCnDEC3_SRC ISRCnDEC4_SRC ISRCnDEC2_SRC ISRC1 DEC1 (A4h) ISRC2 DEC1 (ACh) ISRC3 DEC1 (B4h) ISRC1 DEC2 (A5h) ISRC2 DEC2 (ADh) ISRC3 DEC2 (B5h) ISRC1 DEC3 (A6h) ISRC2 DEC3 (AEh) ISRC3 DEC3 (B6h) ISRC1 DEC4 (A7h) ISRC2 DEC4 (AFh) ISRC3 DEC4 (B7h) ISRCn_FSL ISRCn_FSH The ISRC provides synchronous conversion between two sample rates on either the SYSCLK or ASYNCCLK domain. ISRCn_FSL identifies the lower of the two sample rates. ISRCn_FSH identifies the higher of the two sample rates. Both sample rates must be referenced to the same clock domain (SYSCLK or ASYNCCLK). Figure 41 Isochronous Sample Rate Converters (ISRCs) |
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