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PCA1603U/7 데이터시트(PDF) 4 Page - NXP Semiconductors

부품명 PCA1603U/7
상세설명  32 kHz oscillator, amplitude regulated with excellent frequency stability
PDF  16 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCA1603U/7 데이터시트(HTML) 4 Page - NXP Semiconductors

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1997 Dec 12
4
Philips Semiconductors
Product specification
32 kHz watch circuits with EEPROM
PCA16xx series
Time calibration
Taking a normal quartz crystal with frequency 32768kHz,
frequency deviation (
∆f/f) of ±15 × 10−6 and CL = 8.2 pF;
the oscillator frequency is offset (by using non-symmetrical
internal oscillator input and output capacitances of 10 pF
and 15 pF) such that the frequency deviation is
positive-only. This positive deviation can then be
compensated for to maintain time-keeping accuracy.
Once the positive frequency deviation is measured, a
corresponding number ‘n’ (see Table 1) is programmed
into the device’s EEPROM. This causes n pulses of
frequency 8192 Hz to be inhibited every minute of
operation, which achieves the required calibration.
The programming circuit is shown in Fig.2. The required
number n is programmed into EEPROM by varying VDD
according to the steps shown in Fig.3, which are
explained below:
1. The positive quartz frequency deviation (
∆f/f) is
measured, and the corresponding values of n are
found according to Table 1.
2. VDD is increased to 5.1 V allowing the contents of the
EEPROM to be checked from the motor pulse period
tT3 at nominal frequency.
3. VDD is decreased to 2.5 V during a motor pulse to
initialize a storing sequence.
4. The first VDD pulse to 5.1 V erases the contents of
EEPROM.
5. When the EEPROM is erased a logic 1 is at the TEST
pin.
6. VDD is increased to 5.1 V to read the data by pulsing
VDD n times to 4.5 V. After the n edge, VDD is
decreased to 2.5 V.
7. VDD is increased to 5.1 V to store n bits in the
EEPROM.
8. VDD is decreased to 2.5 V to terminate the storing
sequence and to return to operating mode.
9. VDD is increased to 5.1 V to check writing from the
motor pulse period tT3.
10. VDD is decreased to the operation voltage between
two motor pulses to return to operating mode.
(Decreasing VDD during the motor pulse would restart
the programming mode).
The time calibration can be reprogrammed up to 100
times.
Table 1
Quartz crystal frequency deviation, n and tT3
Notes
1. Increments of 2.03
× 10−6/step.
2. Increments of 122
µs/step.
FREQUENCY
DEVIATION
∆f/f
(
× 10−6)
NUMBER OF
PULSES
(n)
tT3
(ms)
0(1)
0
31.250(2)
+2.03
1
31.372
+4.06
2
31.494
..
.
..
.
..
.
+127.89
63
38.936
Fig.2 Circuit for programming the time calibration.
MSA975
VDD
M1
M2
RESET
VSS
TEST
OSC IN
OSC OUT
M
PCA16xx
SERIES
1
2
3
4
8
7
6
5
32 kHz
SIGNAL GENERATOR



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