PCA1603USLASH7 datasheet(3/16 Pages) PHILIPS

3 / 16 page

1997 Dec 12

Philips Semiconductors

Product speciﬁcation

32 kHz watch circuits with EEPROM

PCA16xx series

PINNING

SYMBOL

DESCRIPTION

VSS

ground (0 V)

TEST

test output

OSC IN

oscillator input

OSC OUT

oscillator output

VDD

positive supply voltage

motor 1 output

motor 2 output

RESET

reset input

Fig.1 Pin configuration, PCA16xxT, (PMFP8).

PCA16xxT

VSS

TEST

OSC IN

OSC OUT

RESET

VDD

MSA973

FUNCTIONAL DESCRIPTION AND TESTING

Motor pulse

The motor pulse width (tP) and the cycle times (tT) are

given in Chapter “Available types”.

Voltage level detector

The supply voltage is compared with the internal voltage

reference VLIT and VEOL every minute. The first voltage

level detection is carried out 30 ms after a RESET.

Lithium mode

If a lithium voltage is detected (VDD ≥ VLIT), the circuit will

operate in the lithium mode. The motor pulse will be

produced with a 75% duty factor.

Silver-oxide mode

If the voltage level detected is between VLIT and VEOL, the

circuit will operate in silver-oxide mode.

Battery end-of-life(1)

If the battery end-of-life is detected (VDD ≤ VEOL), the

motor pulse will be produced without chopping. To indicate

this condition, bursts of 4 pulses are produced every 4 s.

Power-on reset

For correct operation of the Power-on reset the rise time of

VDD from 0 V to 2.1 V should be less than 0.1 ms.

All resettable flip-flops are reset. Additionally the polarity of

the first motor pulse is positive: VM1 − VM2 ≥ 0V.

(1) Only available for types with a 1 s motor pulse.

Customer testing

An output frequency of 32 Hz is provided at RESET (pin 8)

to be used for exact frequency measurement. Every

minute a jitter occurs as a result of time calibration, which

occurs 90 to 150 ms after disconnecting the RESET from

VDD.

Connecting the RESET to VDD stops the motor pulses

leaving them in a HIGH impedance 3-state condition and a

32 Hz signal without jitter is produced at the TEST pin.

A debounce circuit protects accidental stoppages due to

mechanical shock to the watch (tDEB = 14.7 to 123.2 ms).

Connecting RESET to VSS activates Tests 1 and 2 and

disables the time calibration.

Test 1, VDD >VEOL. Normal function takes place except

the voltage detection cycle (tV) is 125 ms and the cycle

time tT1 is 31.25 ms. At pin TEST a minute signal is

available at 8192 times its normal frequency.

Test 2(2), VDD <VEOL. The voltage detection cycle (tV) is

31.25 ms and the motor pulse period (tT2) = 31.25 ms.

Test and reset mode are terminated by disconnecting the

RESET pin.

Test 3, VDD > 5.1 V. Motor pulses with a time period of

tT3 = 31.25 ms and n × 122 µs are produced to check the

contents of the EEPROM. At pin TEST the motor pulse

period signal (tT) is available at 1024 times its normal

frequency. The circuit returns to normal operation when

VDD < 2.5 V between two motor pulses.

(2) Only applicable for types with the battery end-of-life detector.

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