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P83C266BDR 데이터시트(PDF) 54 Page - NXP Semiconductors

부품명 P83C266BDR
상세설명  80C51 8-bit CPU
PDF  92 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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1999 Mar 10
54
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.4
OSD clock generator
The clock generator comprises Phase-Locked-Loop circuitry. The frequency of the OSD clock is programmable and is
determined by the decimal value of the contents of the 8-bit OSPLL register. OSD clock frequencies within the range
4 to 12 MHz can be selected in increments of 31.25 kHz. The OSD frequency (fOSD) is calculated as shown below:
Where fHSYNCP is the horizontal sync frequency after the polarity selection circuit.
17.4.1
OSD PLL REGISTER (OSPLL)
The reset value of OSPLL is 00H.
Table 62 OSD PLL Register (SFR address C4H)
Table 63 Description of OSPLL bits
Table 64 Selection of OSD clock frequency
76543210
PLL7
PLL6
PLL5
PLL4
PLL3
PLL2
PLL1
PLL0
BIT
SYMBOL
DESCRIPTION
7 to 0
PLL7 to PLL0 These 8 bits are used to select the OSD clock frequency. Examples of OSD clock
selection are shown in Table 64.
OSPLL VALUE
OSD FREQUENCY (MHz)
00H
4.00
3FH
6.00
7FH
8.00
BFH
10.00
FFH
12.00
f
OSD
2f
HSYNCP
129
OSPLL value
+
()
×
×
=
Fig.33 OSD PLL.
handbook, halfpage
MGM681
OSPLL
(C4H)
DIVIDER
SYSCLK
÷2
fOSD
HSYNC
PLL
HSYNCP
LOAD_SFR
RESET
DI



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