WM8753LEBSLASHV datasheet(60/87 Pages) WOLFSON

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Advanced Information

WM8753L

AI Rev 3.1 June 2004

PMS selects Voice audio interface operation in master or slave mode. In Master mode VXCLK and

VXFS are outputs. The frequency of FS is set by the sample rate control bits SRMODE and PSR. In

Slave mode VXCLK and VXFS are inputs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ADCDOP

ADC

data

output

ADCDAT

and

VXDOUT enable

0 = ADC data output to ADCDAT or

VXDOUT as selected by IFMODE[1:0]

1 = ADC data output to ADCDAT and

VXDOUT

VXCLKINV

VXCLK invert bit (for master and slave

modes)

0 = VXCLK not inverted

1 = VXCLK inverted

PMS

Voice Interface Master / Slave Mode

Control

1 = Enable Master Mode

0 = Enable Slave Mode

MONO

Mono ADC data only

1 = output left channel ADC data only

0 = output left and right ADC data

Vx DAC and ADC right, left and I

modes VXCLK polarity

1 = invert VXCLK polarity

0 = normal VXCLK polarity

PLRP

Vx DAC and ADC DSP Mode – mode

A/B select

1 = MSB is available on 1

st VXCLK rising

edge after VXFS rising edge (mode B)

0 = MSB is available on 2

nd VXCLK

rising edge after VXFS rising edge

(mode A)

3:2

PWL[1:0]

Vx DAC and ADC Audio Data Word

Length

11 = 32 bits (see Note)

10 = 24 bits

01 = 20 bits

00 = 16 bits

R3 (03h)

Digital Voice

Audio

Interface

Format

1:0

PFORMAT[1:

Vx DAC and ADC Audio Data Format

Select

11 = DSP Mode

10 = I

2S Format

01 = Left justified

00 = Right justified

Table 55 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data.

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