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WM8753LEB/V 데이터시트(PDF) 15 Page - Wolfson Microelectronics plc

부품명 WM8753LEB/V
상세설명  HI FI AND TELEPHONY DUAL CODEC
PDF  87 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8753LEB/V 데이터시트(HTML) 15 Page - Wolfson Microelectronics plc

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WM8753L
Advanced Information
w
AI Rev 3.1 June 2004
15
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25
oC,
Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK / VXCLK cycle time
tBCY
50
ns
BCLK / VXCLK pulse width high
tBCH
20
ns
BCLK / VXCLK pulse width low
tBCL
20
ns
LRC / VXFS set-up time to BCLK / VXCLK rising edge
tLRSU
10
ns
LRC / VXFS hold time from BCLK / VXCLK rising edge
tLRH
10
ns
DACDAT / VXDIN hold time from BCLK / VXCLK rising
edge
tDH
10
ns
ADCDAT / VXDOUT propagation delay from BCLK /
VXCLK falling edge
tDD
10
ns
Note:
1.
BCLK / VXCLK period should always be greater than or equal to MCLK / VXCLK period.



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