WM9711 datasheet(43/66 Pages) WOLFSON

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Production Data

WM9711L

PD Rev 4.1 April 2004

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

IRQ INV

Inverts the IRQ signal (pin 45)

0: IRQ signal not inverted

1: IRQ signal inverted

58h

Additional

Functional

Control

WAKEEN

Enables GPIO wake-up

0: Disabled

1: Enabled

Table 30 Additional Functionality for GPIO Pins

POWER MANAGEMENT

The WM9711L includes the standard power down control register defined by the AC’97 specification

(register 26h). Additionally, it also allows more specific control over the individual blocks of the device

through register 24h. Each particular circuit block is ON when both the relevant bit in register 26h and

the relevant bit in register 24h are set to ‘0’.

DEFAULT

ADDRESS

BIT

LABEL

NORMAL

PIN 47 ‘HI’

DURING

RESET

DESCRIPTION

PR6

0 (ON)

1 (OFF)

Disables HPOUTL, HPOUTR and

OUT3 Buffer

PR5

0 (ON)

1 (OFF)

Disables internal clock

PR4

0 (ON)

1 (OFF)

Disables AC-link interface

(external clock off)

PR3

0 (ON)

1 (OFF)

Disables VREF, analogue mixers

and outputs

PR2

0 (ON)

1 (OFF)

Disables analogue mixers,

LOUT2, ROUT2 (but not VREF)

PR1

0 (ON)

1 (OFF)

Disables stereo DAC

PR0

0 (ON)

1 (OFF)

Disables audio ADCs and input

Mux

REF

Read-only bit, indicates VREF is

ready (inverse of PR2)

ANL

Read-only bit, indicates analogue

mixers are ready (inverse of PR3)

DAC

Read-only bit, indicates audio

DACs are ready (inverse of PR1)

26h

Powerdown/

Status

ADC

Read-only bit, indicates audio

ADCs are ready (inverse of PR0)

Table 31 Powerdown and Status Register (Conforms to AC’97 Rev 2.2)

As can be seen from the table above, most blocks are ‘ON’ by default. However, if pin 47

(GPIO4/ADA/MASK) is held high during reset, the WM9711L starts up with all blocks powered down

by default, saving power. This is achieved by connecting a pull-up resistor (e.g. 100k

Ω) from pin 47

to DBVDD. Note that the state of pin 47 during reset only affects register 26h.

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