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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM9711 데이터시트(PDF) 54 Page - Wolfson Microelectronics plc |
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WM9711 데이터시트(HTML) 54 Page - Wolfson Microelectronics plc |
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54 / 66 page  WM9711L Production Data w PD Rev 4.1 April 2004 54 Register 1Ch controls the recording gain. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 15 RMU 1 (mute) Mutes audio ADC input 14 GRL 0 (standard) Selects gain range for PGA of left ADC. 0=0...+22.5dB in 1.5dB steps, 1=-17.25...+30dB in 0.75dB steps 13:8 RECVOLL 000000 (0dB) Controls left ADC recording volume 7 ZC 0 (OFF) Enables zero-cross detector 6 GRR 0 (standard) Selects gain range for PGA of left ADC. 0=0...+22.5dB in 1.5dB steps, 1=-17.25...+30dB in 0.75dB steps 1Ch 5:0 RECVOLR 000000 (0dB) Controls right ADC recording volume Audio ADC, Record Gain Register 20h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the WM9711L. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 13 3DE 0 (OFF) Enables 3D enhancement Audio DACs, 3D Stereo Enhancement 20h 7 LB 0 (OFF) Enables loopback (i.e. feed ADC output data directly into DAC) Intel’s AC’97 Component Specification, Revision 2.2, page 55 Register 22h controls 3D stereo enhancement for the audio DACs. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 5 3DLC 0 (low) Selects lower cut-off frequency 4 3DUC 0 (high) Selects upper cut-off frequency 22h 3:0 3DDEPTH 0000 (0%) Controls depth of 3D effect Audio DACs, 3D Stereo Enhancement Register 24h is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 24h AND register 26h. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 15 PD15 0 * Disables Crystal Oscillator 14 PD14 0 * Disables left audio DAC 13 PD13 0 * Disables right audio DAC 12 PD12 0 * Disables left audio ADC 11 PD11 0 * Disables right audio ADC 10 PD10 0 * Disables MICBIAS 9 PD9 0 * Disables left headphone mixer 8 PD8 0 * Disables right headphone mixer 7 PD7 0 * Disables speaker mixer 6 PD6 0 * Disables MONO_OUT buffer (pin 33) and phone mixer 5 PD5 0 * Disables OUT3 buffer (pin 37) 4 PD4 0 * Disables headphone buffers (HPOUTL/R) 3 PD3 0 * Disables speaker outputs (LOUT2, ROUT2) 2 PD2 0 * Disables Line Input PGA (left and right) 1 PD1 0 * Disables Phone Input PGA 24h 0 PD0 0 * Disables Mic Input PGA (left and right) Power Management * “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0. |
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