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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM98501CCVBH 데이터시트(PDF) 19 Page - National Semiconductor (TI) |
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LM98501CCVBH 데이터시트(HTML) 19 Page - National Semiconductor (TI) |
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19 / 24 page  Register Data (Continued) Bit Bit Symbol Description [3] Offset Auto-Calibration Enable Enables the digital black level correction loop. Analog offset registers are read-only when offset auto-calibration is enabled. [2] SHP/SHD Active-HIGH Enable Inverts the SHP and SHD inputs causing the CDS to sample on the rising edges of SHP and SHD. Sampling is performed on the falling edges of SHP and SHD when the signals are Active-low. [1] CDS Enable (AUX-In Disable) Instructs the CDS to sample the CCD input. Otherwise, the AUX In input is sampled in sample-and-hold mode. [0] Analog Power Down Cuts power to the on-chip analog circuitry including the CDS, PGA, ADC, and bandgap references. Register Name Software Control 1 (Customer) Address D Hex Type Read/Write Reset Value XX00 0X00 Binary Bit Bit Symbol Description [5:4] Analog Output Select Routes the selected internal analog signal to the differential analog output pins AOUT+ and AOUT−. 00 CDS 01 PGA Stage 1 10 PGA Stage 2 11 PGA Stage 3 [3] Analog Output Enable Enables the differential analog output pins AOUT+ and AOUT−. If the analog outputs are disabled, the pins should not be loaded. [1] ADC Reference Select Reference biasing selection for the analog-to-digital converter. 0 Passive Biasing (Resistors) 1 Active Biasing (Bandgap) [0] DAC Reference Select Reference biasing selection for the digital-to-analog converter. 0 Active Biasing (Bandgap) 1 Passive Biasing (Resistors) Register Name Power Level Control 0 Address E Hex Type Read/Write Reset Value 1010 1010 Binary Bit Bit Symbol Description [7:6] PGA Stage 1 Amplifier Bias Adjusts the power level of the PGA stage 1 amplifier. The power level is relative to the value of the binary number stored. [5:4] PGA Common-Mode Input Bias Adjusts the power level of the PGA common-mode input. The power level is relative to the value of the binary number stored. [3:2] CDS Amplifier Bias Adjusts the power level of the CDS amplifier. The power level is relative to the value of the binary number stored. [1:0] CDS Common-Mode Input Bias Adjusts the power level of the CDS common-mode input. The power level is relative to the value of the binary number stored. Register Name Power Level Control 1 Address F Hex Type Read/Write Reset Value 0101 1010 Binary Bit Bit Symbol Description [7:6] ADC Coarse Bank Bias Adjusts the power level of the ADC coarse bank. The power level is relative to the value of the binary number stored. [5:4] ADC Fine Bank Bias Adjusts the power level of the ADC fine bank. The power level is relative to the value of the binary number stored. [3:2] PGA Stage 3 Amplifier Bias Adjusts the power level of the PGA stage 3 amplifier. The power level is relative to the value of the binary number stored. [1:0] PGA Stage 2 Amplifier Bias Adjusts the power level of the PGA stage 2 amplifier. The power level is relative to the value of the binary number stored. www.national.com 19 |
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