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DS21352 데이터시트(PDF) 91 Page - Dallas Semiconductor |
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DS21352 데이터시트(HTML) 91 Page - Dallas Semiconductor |
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91 / 137 page ![]() DS21352/DS21552 91 of 137 Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552 Note: The 68uf cap is required to maintain VDD during a transient event. COMPONET DESCRIPTION D1 – D4 Schottky Diode, International Rectifier 11DQ04 C1 0.1uf ceramic in parallel with 10uf tantalum C2 .47 uf, non polarized ceramic construction S Semtech LC01-6, 6V low capacitance TVS Fuse Rt Rterm R1, R2, R3, R4 X1 X2 For more information on the selection of these components see the separate application notes on Secondary Over Voltage Protection and T1 Network Interface Design Criteria. These applications notes are available from Dallas Semiconductor’s Web site at www.dalsemi.com RTIP RRING TTIP TRING Receive Line DS21552 1.544MHz MCLK +VDD S C1 D1 D2 D3 D4 1:1 Fuse Fuse Transmit Line Fuse Fuse 0.1uF N:1 470 470 DVDD DVSS 0.1uF RVDD RVSS 0.1uF TVDD TVSS 0.1uF +5V 0.01uF 68uf C2 R1 R2 R3 R4 Rt Rt Rterm Rterm X1 X2 + |
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