DS21352 datasheet(41/137 Pages) DALLAS

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DS21352/DS21552

41 of 137

CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)

(MSB)

(LSB)

RJC

RESA

TESA

RCM4

RCM3

RCM2

RCM1

RCM0

SYMBOL

POSITION

NAME AND DESCRIPTION

RJC

CCR6.7

Receive Japanese CRC6 Enable.

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)

1 = use Japanese standard JT–G704 CRC6 calculation

RESA

CCR6.6

Receive Elastic Store Align. Setting this bit from a zero to a one will force the receive

elastic store’s write/read pointers to a minimum separation of half a frame. No action

will be taken if the pointer separation is already greater or equal to half a frame. If

pointer separation is less than half a frame, the command will be executed and the data

will be disrupted. Should be toggled after RSYSCLK has been applied and is stable.

Must be cleared and set again for a subsequent align. See section 14.3 for details.

TESA

CCR6.5

Transmit Elastic Store Align. Setting this bit from a zero to a one will force the

transmit elastic store’s write/read pointers to a minimum separation of half a frame. No

action will be taken if the pointer separation is already greater or equal to half a frame.

If pointer separation is less than half a frame, the command will be executed and the

data will be disrupted. Should be toggled after TSYSCLK has been applied and is

stable. Must be cleared and set again for a subsequent align. See section 14.3 for details.

RCM4

CCR6.4

Receive Channel Monitor Bit 4. MSB of a channel decode that determines which

receive channel data will appear in the RDS0M register. See Section 9 for details.

RCM3

CCR6.3

Receive Channel Monitor Bit 3.

RCM2

CCR6.2

Receive Channel Monitor Bit 2.

RCM1

CCR6.1

Receive Channel Monitor Bit 1.

RCM0

CCR6.0

Receive Channel Monitor Bit 0. LSB of the channel decode.

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