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WM8521

w

PP Rev 1.3 December 2004

11

In I

LRCLK is low during the left samples and high during the right samples.

MSB

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

DIN

3

3

12

3

12

n

n-2 n-1

n

n-2 n-1

1 BCLK

1 BCLK

LSB

MSB

LSB

1/fs

Figure 3 I

RIGHT JUSTIFIED MODE INPUT FORMAT

The WM8521 supports word lengths of up to 16-bits in right justified mode. If a word length shorter

than 16-bits is used, the unused bits should be padded with zeroes.

In right justified mode, LRCLK must be high for a minimum of 16 BCLKs and low for a minimum of

16 BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirement is met.

The digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCLK

indicating whether the left or right channel is present. LRCLK is also used as a timing reference to

indicate the beginning or end of the data words.

In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.

LRCLK is high during the left samples and low during the right samples.

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

DIN

1/fs

MSB

3

3

12

14 15 16

LSB

MSB

3

3

12

14 15 16

LSB

Figure 4 Right Justified Mode Timing Diagram

DSP MODE INPUT FORMAT

A DSP compatible, time division multiplexed format is also supported by the WM8521.

This format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of 16 bit

word length. The ‘synch’ pulse replaces the normal duration LRCLK, and DSP mode is auto-detected

by the shorter than normal duration of the LRCLK. If LRCLK is of 4 BCLK or less duration, the DSP

compatible format is selected. Early and Late clock formats are supported, selected by the state of

the FORMAT pin.