WM8521

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PP Rev 1.3 December 2004

12

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

DIN

1/fs

MSB

12

15 16

LSB

12

15 16

MSB

1

Max 4 BCLKs

NO VALID DATA

Input Word Length (16 bits)

Figure 5 DSP ‘Late’ Mode Timing

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

DIN

1/fs

MSB

12

15 16

LSB

12

15 16

Max 4 BCLKs

NO VALID DATA

Input Word Length (16 bits)

1 BCLK

1 BCLK

Figure 6 DSP ‘Early’ Mode Timing

AUDIO DATA SAMPLING RATES

The master clock for WM8521 supports audio sampling rates from 256fs to 768fs, where fs is the

audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is

used to operate the digital filters and the noise shaping circuits.

The WM8521 has a master clock detection circuit that automatically determines the relationship

between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If there is

a greater than 32 clocks error, the master clock defaults to 768fs. The master clock should be

synchronised with LRCLK, although the WM8521 is tolerant of phase differences or jitter on this

clock.

MASTER CLOCK FREQUENCY (MHz) (MCLK)

SAMPLING

RATE

(LRCLK)

256fs

384fs

512fs

768fs

32kHz

8.192

12.288

16.384

24.576

44.1kHz

11.2896

16.9344

22.5792

33.8688

48kHz

12.288

18.432

24.576

36.864

96kHz

24.576

36.864

Unavailable

Unavailable

Table 1 Master Clock Frequencies Versus Sampling Rate

Note:

For sample rates down to 8k, scale MCLK accordingly.