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WM8510GEDS/V 데이터시트(PDF) 45 Page - Wolfson Microelectronics plc

부품명 WM8510GEDS/V
상세설명  MONO CODEC WITH SPEAKER DRIVER
PDF  56 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
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WM8510GEDS/V 데이터시트(HTML) 45 Page - Wolfson Microelectronics plc

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WM8510
w
PP Rev 1.2 December 2004
45
The PLL frequency ratio R = f2/f1 (see Figure 27) can be set using the register bits PLLK and PLLN:
PLLN = int R
PLLK = int (2
24 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 2
24 x (8.192 – 8)) = 3221225 = 3126E9h
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
4
PLLPRESCALE
0
Divide MCLK by 2 before input to
PLL
R36
PLL N value
3:0
PLLN
1000
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R37
PLL K value 1
5:0
PLLK [23:18]
0Ch
R38
PLL K Value 2
8:0
PLLK [17:9]
093h
R39
PLL K Value 3
8:0
PLLK [8:0]
0E9h
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
Table 30 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown.
MCLK
(MHz)
(F1)
DESIRED
OUTPUT
(MHz)
F2
(MHz)
PRESCALE
DIVIDE
POSTSCALE
DIVIDE
R
N
(Hex)
K
(Hex)
12
11.29
90.3168
1
2
7.5264
7
86C227
12
12.288
98.304
1
2
8.192
8
3126E9
13
11.29
90.3168
1
2
6.947446
6
F28BD5
13
12.288
98.304
1
2
7.561846
7
8FD526
14.4
11.29
90.3168
1
2
6.272
6
45A1CB
14.4
12.288
98.304
1
2
6.826667
6
D3A06D
19.2
11.29
90.3168
2
2
9.408
9
6872B0
19.2
12.288
98.304
2
2
10.24
A
3D70A4
19.68
11.29
90.3168
2
2
9.178537
9
2DB493
19.68
12.288
98.304
2
2
9.990243
9
FD80A0
19.8
11.29
90.3168
2
2
9.122909
9
1F76F8
19.8
12.288
98.304
2
2
9.929697
9
EE009F
24
11.29
90.3168
2
2
7.5264
7
86C227
24
12.288
98.304
2
2
8.192
8
3126E9
26
11.29
90.3168
2
2
6.947446
6
F28BD5
26
12.288
98.304
2
2
7.561846
7
8FD526
27
11.29
90.3168
2
2
6.690133
6
BOAC94
27
12.288
98.304
2
2
7.281778
7
482297
Table 31 PLL Frequency Examples



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