MPC855 datasheet(68/76 Pages) MOTOROLA

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MPC860 Family Hardware Speciﬁcations

MOTOROLA

MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Figure 13-71 shows the MII transmit signal timing diagram.

Figure 13-71. MII Transmit Signal Timing Diagram

13.3 MII Async Inputs Signal Timing (MII_CRS,

MII_COL)

Table 13-29 provides information on the MII async inputs signal timing.

Figure 13-72 shows the MII asynchronous inputs signal timing diagram.

Figure 13-72. MII Async Inputs Timing Diagram

Table 13-28. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

—

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

—

MII_TX_CLK pulse width high

65%

MII_TX_CLK

period

MII_TX_CLK pulse width low

35%

65%

MII_TX_CLK

period

Table 13-29. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK

period

MII_TX_CLK (Input)

MII_TXD[3:0] (Outputs)

MII_TX_EN

MII_TX_ER

MII_CRS, MII_COL

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