TABLE 3. The F

RF R[19]

IF R[19]

RF R[20]

IF R[20]

F

(RF LD)

(IF LD)

(RF F

(IF F

0000

Disabled (Note 12)

0100

IF Lock Detect (Note 13)

1000

RF Lock Detect (Note 13)

1100

RF/IF Lock Detect (Note 13)

X

0

0

1

IF Reference Divider Output

X

0

1

0

RF Reference Divider Output

X

1

0

1

IF Programmable Divider Output

X

1

1

0

RF Programmable Divider Output

0011

Fastlock (Note 14)

0111

IF Counter Reset (Note 15)

1011

RF Counter Reset (Note 15)

1111

IF and RF Counter Reset (Note 15)

X = don’t care condition

Note 13: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output

is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.

occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).

Note 15: The IF Counter Reset mode resets IF PLL’s R and N counters and brings IF charge pump output to a TRI-STATE condition. The RF Counter Reset mode

resets RF PLL’s R and N counters and brings RF charge pump output to a TRI-STATE condition. The IF and RF Counter Reset mode resets all counters and brings

both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits then N counter resumes counting in “close” alignment with the R counter. (The

maximum error is one prescaler cycle.)

POWERDOWN OPERATION

Synchronous and asynchronous powerdown modes are

both available by MICROWIRE selection. Synchronously

powerdown occurs if the respective loop’s R18 bit (Do

TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI.

Asynchronous powerdown occurs if the loop’s R18 bit is HI

when its N20 bit becomes HI.

In the synchronous powerdown mode, the powerdown func-

tion is gated by the charge pump to prevent unwanted fre-

quency jumps. Once the powerdown program bit N20 is

loaded, the part will go into powerdown mode when the

charge pump reaches a TRI-STATE condition.

In the asynchronous powerdown mode, the device powers

down immediately after the LE pin latches in a HI condition

on the powerdown bit N20.

Activation of either the IF or RF PLL powerdown conditions

in either synchronous or asynchronous modes forces the re-

spective loop’s R and N dividers to their load state condition

and debiasing of its respective f

state. The oscillator circuitry function does not become dis-

abled until both IF and RF powerdown bits are activated. The

MICROWIRE control register remains active and capable of

loading and latching data during all of the powerdown

modes.

The device returns to an actively powered up condition in ei-

ther synchronous or asynchronous modes immediately upon

LE latching LOW data into bit N20.

Powerdown Mode Select Table

R18

N20

Powerdown Status

0

0

PLL Active

1

0

PLL Active

(Charge Pump Output TRI-STATE)

0

1

Synchronous Powerdown Initiated

1

1

Asynchronous Powerdown Initiated

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