Programmable Reference Divider (R-Counter)

If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 6-bit R-counter. The serial

data format is shown below.

MSB

REGISTER’S BIT MAPPING

LSB

19

18

17

16

15

14

13

12

11

10

9876543210

RESERVED

R-COUNTER’s Divide Ratio

C2

C1

X

XXXXXXX

XXXX

R6

R5

R4

R3

R2

R1

1

0

Note: X = Don’t Care Condition

Reference Counter Divide Ratio (R-Counter)

Divide Ratio, R

R6

R5

R4

R3

R2

R1

3

000011

4

000100

*

******

63

111111

Note: Divide ratio must be from 3 to 63.

Pulse Swallow Function

Output frequency of external voltage controlled oscillator (VCO)

B:

Preset divide ratio of binary 6-bit programmable counter (3 to 63)

A:

Preset divide ratio of binary 6-bit swallow counter (0

≤ A ≤ P, A ≤ B)

R:

Preset divide ratio of binary 6-bit programmable reference counter (3 to 63)

P:

Preset modulus of dual modulus prescaler (32 or 64)

Receiver Functional Description

The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation cir-

cuit, doubler, and voltage regulator for an external LNA stage are shown.

DS012815-5

Note: The receiver can be powered down, either by hardware through the Rx PD pin, or by software through the programming of F6 bit in F-Latch. The power

down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.)

www.national.com

9