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FT121Q-R 데이터시트(PDF) 23 Page - Future Technology Devices International Ltd.

부품명 FT121Q-R
상세설명  Enhanced USB Device Controller with SPI Slave IC
PDF  46 Pages
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제조업체  FTDI [Future Technology Devices International Ltd.]
홈페이지  http://www.ftdichip.com
Logo FTDI - Future Technology Devices International Ltd.

FT121Q-R 데이터시트(HTML) 23 Page - Future Technology Devices International Ltd.

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Copyright © 2014 Future Technology Devices International Limited
23
Document No.: FT_000648
FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC
Datasheet Version 1.2
Clearance No.: FTDI#
312
Bit
Symbol
Reset
Description
2
Clock Running
1
0: internal clocks stop during USB suspend
1: internal clocks continue running during USB suspend
This bit must be set to ‘0’ for bus powered application in
order to meet the USB suspend current requirement.
Note: The programmed value will not be changed by a
bus reset.
3
Interrupt Mode
1
0: interrupt will not generate on NAK or Error
transactions
1: interrupt will generate on NAK and Error transactions
Note: The programmed value will not be changed by a
bus reset.
4
DP_Pullup
0
0: Pullup resistor on DP pin disabled
1: Pullup resistor on DP pin enabled when Vbus is
present
Note: The programmed value will not be changed by a
bus reset.
5
Reserved
0
Reserved, write to 0
7-6
Endpoint Configuration
Mode
0b’00
Set the endpoint configuration mode for EP2.
00: Mode 0 (Non-ISO Mode)
01: Mode 1 (ISO-OUT Mode)
10: Mode 2 (ISO-IN Mode)
11: Mode 3 (ISO-IO Mode)
In Enhanced Mode, these 2 bits are reserved. The
Endpoint Configuration will be done through separate
command. See “Set Endpoint Configuration” commands.
Table 6.5 Configuration Register (Byte 1)
Bit
Symbol
Reset
Description
3-0
Reserved
0b’1011
Reserved, write to 0b’1111
5-4
Reserved
0b’00
Reserved, write to 0
6
SET_TO_ONE
0
This bit must be set to 1
7
SOF-only Interrupt
Mode
0
0: normal operation
1: interrupt will generate on receiving SOF packet only,
regardless of the value of the Interrupt Pin Mode bit in
the Interrupt configuration register.
Table 6.6 Configuration Register (Byte 2)



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