AM29LV642D datasheet(10/53 Pages) AMD

10 / 53 page

Am29LV642D

P R E L I M I NARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1.

Am29LV642D Device Bus Operations

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

IN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at

the same time.

2. Addresses are A21:A0. Sector addresses are A21:A15.

3. D

IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

5. All sectors are unprotected when shipped from the factory.

VersatileI/O

 (V

IO) Control

The VersatileI/O (V

IO) control allows the host system

to set the voltage levels that the device generates at

its data outputs and the voltages tolerated at its data

inputs to the same voltage level that is asserted on the

IO pin. This allows the device to operate in 1.8 V, 3 V,

or 5 V system environment as required. For voltage

levels below 3 V, contact an AMD representative for

more information.

For example, a V

I/O of 4.5–5.5 volts allows for I/O at

the 5 volt level, driving and receiving signals to and

from other 5 V devices on the same bus.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# or CE2# and OE# pins to V

IL. CE# or

CE2# is the power control and selects the device. OE#

is the output control and gates array data to the output

pins. WE# should remain at V

IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

Operation

CE#

(Note 1)

OE#

WE#

RESET#

ACC

Addresses

(Note 2)

DQ0–DQ15

Read

OUT

Write (Program/Erase)

AIN

(Note 3)

Accelerated Program

(Note 3)

Standby

VCC ± 0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Group Protect (Note 4)

VID

SA, A6 = L,

A1 = H, A0 = L

(Note 3)

Sector Group Unprotect

(Note 4)

VID

SA, A6 = H,

A1 = H, A0 = L

(Note 3)

Temporary Sector Group

Unprotect

VID

AIN

(Note 3)

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