NSC800D datasheet(48/76 Pages) NSC

48 / 76 page

129 Rotate and Shift (Continued)

Rotate the data in memory location m1 right through the

carry

TLC5171 – 67

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of m1

76543210

RR (HL)

00011110

Timing

M cycles

T states

15 (4 4 4 3)

Addressing Mode

3210

RR (IX a d) (for NX e 0)

11NX 11101

RR (IY a d) (for NX e 1)

1011

1110

Timing

M cycles

T states

23 (4 4 3 5 4 3)

Addressing Mode

Indexed

SLA

Shift the data in memory location m1 left arithmetic

TLC5171 – 68

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 7 of m1

76543210

SLA (HL)

00100110

Timing

M cycles

T states

15 (4 4 4 3)

Addressing Mode

3210

SLA (IX a d) (for NX e 0)

11NX 11101

SLA (IY a d) (for NX e 1)

1011

0110

Timing

M cycles

T states

23 (4 4 3 5 4 3)

Addressing Mode

Indexed

SRA

Shift the data in memory location m1 right arithmetic

TLC5171 – 69

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of m1

76543210

SRA (HL)

00101110

Timing

M cycles

T states

15 (4 4 4 3)

Addressing Mode

3210

SRA (IX a d) (for NX e 0)

11NX 11101

SRA (IY a d) (for NX e 1)

1011

1110

Timing

M cycles

T states

23 (4 4 3 5 4 3)

Addressing Mode

Indexed

SRL

Shift right logical the data in memory location m1

TLC5171 – 70

S Reset

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of m1

NSC800D 데이터시트(PDF) 48 Page - National Semiconductor (TI)

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