PC87309VLJ datasheet(9/192 Pages) NSC

9 / 192 page

Table of Contents

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6.0

Enhanced Serial Port - UART1 (Logical Device 3)

6.1

REGISTER BANK OVERVIEW ............................................................................................... 136

6.2

DETAILED DESCRIPTION ...................................................................................................... 136

6.2.1

16450 or 16550 UART Mode ..................................................................................... 137

6.2.2

Extended UART Mode ............................................................................................... 137

6.3

FIFO TIME-OUTS .................................................................................................................... 137

6.4

AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE .......................................... 138

6.4.1

Transmission Deferral ............................................................................................... 138

6.5

BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS ................................................. 138

6.5.1

Receiver Data Port (RXD) or the Transmitter Data Port (TXD) ................................. 138

6.5.2

Interrupt Enable Register (IER) ................................................................................. 139

6.5.3

Event Identification Register (EIR) ............................................................................ 140

6.5.4

FIFO Control Register (FCR) ..................................................................................... 142

6.5.5

Line Control Register (LCR) and Bank Selection Register (BSR) ............................. 142

6.5.6

Bank Selection Register (BSR) ................................................................................. 143

6.5.7

Modem/Mode Control Register (MCR) ...................................................................... 143

6.5.8

Line Status Register (LSR) ........................................................................................ 144

6.5.9

Modem Status Register (MSR) .................................................................................. 145

6.5.10

Scratchpad Register (SPR) ....................................................................................... 146

6.5.11

Auxiliary Status and Control Register (ASCR) .......................................................... 146

6.6

BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS ......................................... 146

6.6.1

Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), .............................. 147

6.6.2

Line Control Register (LCR) and Bank Select Register (BSR) .................................. 147

6.7

BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................ 148

6.7.1

Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ........................... 148

6.7.2

Extended Control Register 1 (EXCR1) ...................................................................... 149

6.7.3

Line Control Register (LCR) and Bank Select Register (BSR) .................................. 149

6.7.4

Extended Control and Status Register 2 (EXCR2) .................................................... 149

6.7.5

Reserved Register ..................................................................................................... 150

6.7.6

TX_FIFO Current Level Register (TXFLV) ................................................................ 150

6.7.7

RX_FIFO Current Level Register (RXFLV) ............................................................... 150

6.8

BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 150

6.8.1

Module Revision ID Register (MRID) ........................................................................ 151

6.8.2

Shadow of Line Control Register (SH_LCR) ............................................................. 151

6.8.3

Shadow of FIFO Control Register (SH_FCR) ............................................................ 151

6.8.4

Line Control Register (LCR) and Bank Select Register (BSR) .................................. 151

6.9

UART1 REGISTER BITMAPS ................................................................................................. 151

7.0

Power Management (Logical Device 4)

7.1

POWER MANAGEMENT OPTIONS ....................................................................................... 155

7.2

THE POWER MANAGEMENT REGISTERS .......................................................................... 155

7.2.1

Power Management Index Register .......................................................................... 155

7.2.2

Power Management Data Register ........................................................................... 155

7.2.3

Function Enable Register 1 (FER1) ........................................................................... 155

7.2.4

Power Management Control Register (PMC1) .......................................................... 156

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