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PC87309VLJ 데이터시트(PDF) 131 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC87309VLJ
상세설명  PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging
PDF  192 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87309VLJ 데이터시트(HTML) 131 Page - National Semiconductor (TI)

Back Button PC87309VLJ Datasheet HTML 127Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 128Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 129Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 130Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 131Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 132Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 133Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 134Page - National Semiconductor (TI) PC87309VLJ Datasheet HTML 135Page - National Semiconductor (TI) Next Button
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
131
www.national.com
5.19 UART2 WITH IR REGISTER BITMAPS
76543210
Reset
Required
Receiver Data
Register (RXD)
Bank 0,
Received Data
Read Cycles
Offset 00h
76543210
Reset
Required
Transmitter Data
Register (TXD)
Bank 0,
Transmitted Data
Write Cycles
Offset 00h
76543210
Reset
Required
0
0
0
0
0
0
0
0
0
0
LS_IE or TXUR_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
RXHDL_IE
TXLDL_IE
MS_IE
Interrupt Enable
Register (IER)
Bank 0,
Extended Mode
Offset 01h
76543210
Reset
Required
1
0
0
0
0
0
0
0
0
0
Non-Extended Modes, Read Cycles
IPR1 - Interrupt Priority 1
Reserved
Reserved
FEN0 - FIFO Enabled
FEN1 - FIFO Enabled
Event Identification
IPR0 - Interrupt Priority 0
RXFT - RX_FIFO Time-Out
Bank 0,
Register (EIR)
Offset 02h
IPF - Interrupt Pending
76543210
Reset
Required
1
0
0
0
0
0
0
0
0
0
Extended Mode, Read Cycles
Event Identification
Bank 0,
Register (EIR)
DMA_EV
TXEMP-EV
Reserved
Reserved
RXHDL_EV
TXLDL_EV
MS_EV
LS_EV or TXHLT_EV
Offset 02h
76543210
Reset
Required
0
0
0
0
0
0
0
0
0
FIFO Control
Register (FCR)
Bank 0,
RXFTH1
Offset 02h
TXSR
TXFTH0
TXFTH1
RXFTH0
FIFO_EN
RXSR
Reserved
Write Cycles
76543210
Reset
Required
0
0
0
0
0
0
0
0
Link Control
All Banks,
Register (LCR)
Offset 03h
STB
EPS
STKP
SBRK
BKSE
WLS0
WLS1
PEN
76543210
Reset
Required
0
0
0
0
0
0
0
0
Bank Selection
All Banks,
Register (BSR)
Offset 03h
Bank Selected
BKSE-Bank Selection Enable



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