L99MD01 datasheet(27/54 Pages) STMICROELECTRONICS

27 / 54 page

L99MD01

Functional description of the SPI

Doc ID 17242 Rev 6

27/54

For read operations, the <communication error> bit in the <Global Status Byte> is set, but

the register to be read is still transferred to the SDO pin. If the number of clock cycles is

smaller than the frame width, the data at SDO are truncated. If the number of clock cycles is

larger than the frame width, the data at SDO are filled with ‘0’ bits.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.

Note:

As the frame width is 24 bits, an initial Read of <SPI-frame-ID> using a 16 bits

communication sets the <communication Error bit> of the <Global Status Byte>. A

subsequent correct length transaction is necessary to correct this bit.

5.3

Write operation

OC0, OC1: operating code (00 for ‘write’ mode)

The write operation starts with a command byte followed by 2 data bytes.

For write cycles the <Global Status> register is followed by the previous content of the

addressed register.

The RAM memory area consists of 16 bit registers. All unused RAM addresses are read as

‘0’.

Failures are indicated by activating the corresponding bit of the <Global Status> register.

Note:

RAM address 00H is unused. An attempt to access this address is recognized as a

communication line error (‘Data-in stuck to GND’) and all internal registers are cleared

(software reset).

5.4

Read operation

OC0, OC1: operating code (01 for ‘read’ mode)

The read operation starts with a command byte followed by 2 data bytes. The content of the

data bytes is ‘don’t care’. The content of the addressed register is shifted out at SDO within

the same frame (‘in-frame response’).

The returned data byte represents the content of the register to be read.

Failures are indicated by activating the corresponding bit of the <Global Status> register.

5.5

Read and clear status operation

OC0, OC1: operating code (10 for ‘read and clear status’ mode)

The ‘Read and Clear Status’ operation starts with a command byte followed by 2 data bytes.

The content of the data bytes is ‘don’t care’. The content of the addressed status register is

transferred to SDO within the same frame (‘in-frame response’) and is subsequently

cleared.

A ‘Read and Clear Status’ operation with address 3FH clears all Status registers

simultaneously.

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