L99MM70XP datasheet(59/68 Pages) STMICROELECTRONICS

59 / 68 page

L99MM70XP

SPI control and status registers

Doc ID 022637 Rev 2

59/68

Table 40.

Configuration register

Configuration register (3Fh)

Bit

765

Reset state

000

Name

ECV

ECFD

OUT7

OLMASK

OUT1HS

OLMASK

OUT1LS

OLMASK

TW_OL

MASK

TRIG

Table 41.

Configuration register, bits

Bit name

Comment

The bits 15 to 8 of the configuration register have to be written to 0, and read always 0

ECV

ECFD

OUT7

OLMASK

Mask the ECV, ECFD (HS and LS) and OUT7 open-load diagnostics bits (status reg. 2, bits 11, 14,

15):

an open-load event is not considered in the open-load bit (TW_OL) of the global status register

OUT1HS

OLMASK

Mask the OUTHS1 open-load diagnostic bit (status reg. 1/bit 1):

an open-load event (under-current status bit of OUT1HS) is not considered in open-load bit (TW_OL)

of the global status register.

OUT1LS

OLMASK

Mask the OUTLS1 open-load diagnostic bit (status reg. 1/bit 0):

an open-load event (under-current status bit of OUT1LS) is not considered in open-load bit (TW_OL)

of the global status register.

TW_OL

MASK

Mask the TW_OL bit in global status byte:

a temperature warning or open-load event is not considered in the “global error flag”

WDTRIG

Trigger the watchdog.

This bit has to be toggled regularly if the watchdog is active. The watchdog can be triggered either by

this bit or by bit 0 of the Control Register 1.

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