STNRGPF01 datasheet(15/40 Pages) STMICROELECTRONICS

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STNRGPF01

STNRGPF01 block diagram

3.7

Start-up function

The start-up function is divided into two logical parts. The first is the inrush current limiter

and the second part a PFC soft power-on. In Figure 10 the timing of this function is shown.

Figure 10. Start-up function

3.7.1

Inrush current limiter

The device includes the possibility to perform the inrush current limiter function. Pin 21 gives

a CMOS/TTL signal that becomes high after a settable time.

3.7.2

PFC soft power-on

After the inrush current limiter phase the PFC switching activity on the master channel starts

using the integrated function named soft power-on. Thanks to a controlled loop regulation

the PFC output voltage will increase up to the set point (Vout_ref). The soft power-on function

will be activated only in the conditions indicated below:



No load condition. In this case the master channel enters into burst mode regulation.

The PFC output voltage will oscillate between two settable levels (Vburst_min and

Vburst_max). See Figure 11. These levels can be defined during device customization.



Light load condition (below 5%). The PFC operates as in the no load condition.



Load condition (down to 10%). In this case the PFC enters in the run mode and the

output voltage will be regulated to the nominal value Vout_ref. See Figure 11.

When the PFC output voltage is controlled (burst mode or run mode - see conditions 1, 2,

and 3) the soft power-on function will be completed and the PFC_OK pin will be activated.

At the end of this phase the PFC is ready to work at the full load.

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