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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV1647GSTZWT 데이터시트(PDF) 150 Page - Texas Instruments |
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TNETV1647GSTZWT 데이터시트(HTML) 150 Page - Texas Instruments |
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150 / 236 page  TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.11.2.3 ATA/CF Ultra DMA Timing Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing(1) (2) (see Figure 6-28 through Figure 6-37) 1.05 V and 1.2 V NO. MODE UNIT MIN MAX 28 f(SYSCLK5) Operating frequency, SYSCLK5 0-4 25 MHz 0 240 ns 1 160 ns 1 t2CYCTYP Typical sustained average two cycle time 2 120 ns 3 90 ns 4 60 ns 2 tCYC Cycle time, Strobe edge to Strobe edge 0-4 (UDMASTB + 1)P ns Two cycle time, rising to rising edge or falling to 3 t2CYC 0-4 2(UDMASTB + 1)P ns falling edge 0 15 ns 1 10 ns 4 tDS Data setup, data valid before STROBE edge 2-3 7 ns 4 5 ns 5 tDH Data hold, data valid after STROBE edge 0-4 5 ns 0 70 ns 1 48 ns Data valid INPUT setup time, data valid before 2 31 ns STROBE 6 tDVS 3 20 ns 4 6.7 ns Data valid OUTPUT setup time, data valid before 0-4 (UDMASTB)P - 3.5 ns STROBE Data valid INPUT hold time, data valid after 0-4 6.2 ns STROBE 7 tDVH Data valid OUTPUT hold time, data valid after 0-4 1P - 2 ns STROBE CRC word valid setup time at host, CRC valid 10 tCVS 0-4 (UDMASTB)P ns before DMACK negation CRC word valid hold time at sender, CRC valid 11 tCVH 0-4 2P ns after DMACK negation Time from STROBE output released-to-driving 12 tZFS 0-4 0 ns until the first transition of critical timing 0 70 ns 1 48 ns Time from data output released-to-driving until 13 tDZFS 2 31 ns the first transition of critical timing 3 20 ns 4 6.7 ns 0 230 ns 1 200 ns 14 tFS First STROBE time 2 170 ns 3 130 ns 4 120 ns 15 tLI Limited interlock time 0-4 0 150 ns (1) P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns. (2) UDMASTB equals the value programmed in the UDMSTBxP bit field in the UDMASTB register. UDMATRP equals the value programmed in the UDMTRPxP bit field in the UDMATRP register. TENV equals the value programmed in the UDMATNVxP bit field in the UDMATENV register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21). 150 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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