TNETV1647GSTZWT datasheet(74/236 Pages) TI1

74 / 236 page

TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

3.5.2

Multiplexed Pin Configurations

There are numerous multiplexed pins that are shared by more than one peripheral. Some of these pins

are configured by external pullup/pulldown resistors only at reset, and others are configured by software.

As described in detail in Section 3.4.1, Device Configuration at Device Reset, and Section 3.4.2,

Peripheral Selection at Device Reset, hardware configurable multiplexed pins are programmed by external

pullup/pulldown resistors at reset to set the initial functionality of pins for use by a single peripheral. After

reset, software configurable multiplexed pins are programmable through memory mapped registers (MMR)

to allow the switching of pin functionalities during run-time. See Section 3.5.3, Peripheral Selection After

Device Reset, for more details on the register settings.

A summary of the pin multiplexing is shown in Table 3-13. The EMAC peripheral shares pins with the 3.3V

GPIO pins. The VLYNQ pins overlap upper EMIFA address pins resulting in a reduced EMIFA address

range as the VLYNQ width is increased. The ATA peripheral shares data lines and some control signals

with EMIFA. The ATA DMA pins are multiplexed with UART1. The ASP, UART0/1/2, SPI, I2C, and

PWM0/1/2 all default to GPIO pins when not enabled. The VPBE function of the VPSS requires additional

pins to implement the RGB888 mode. These are multiplexed with GPIOs.

Table 3-13. DM6441 Multiplexed Peripheral Pins and Multiplexing Controls

PRIMARY

SECONDARY

TERTIARY

MULTIPLEXED

SECONDARY(1)

TERTIARY(2)

(DEFAULT)

PERIPHERALS

FUNCTION

CONTROL

EMIFA (NAND), HPI EMIFA:

HPI:

PinMux0:HPIEN

EM_A[1] (ALE),

HHWIL, HCNTL0,

Pins:BTSEL[1:0] = 10

EM_A[2] (CLE)

HCS

EM_CS2, EM_CS3

EMIFA, HPI, ATA

EMIFA:

ATA (CF):

HPI:

PinMux0:ATAEN

PinMux0:HPIEN

(CF)

EM_D[0:15],

DD[0:15], DA0

HD[0:15], HINT

EM_BA[0]

EMIFA (NAND),

EMIFA (NAND):

ATA (CF):

HPI:

PinMux0:ATAEN

PinMux0:HPIEN

HPI, ATA (CF)

R/W, EM_WAIT

INTRQ, IORDY,

HR/W, HRDY, HDS1,

(RDY/BSY),

DIOR(IORD) ,

HDS2

EM_OE (RE),

DIOW (IOWR)

EM_WE (WE)

VPBE LCD, GPIO

GPIO:GPIO[0]

VPBE: LCD_OE

PinMux0:LOEEN

VPFE CCD, GPIO

GPIO:GPIO[1]

VPFE: C_WE

PinMux0:CWE

VPBE RGB888,

GPIO:GPIO[2]

VPBE:

PinMux0:RGB888

GPIO

RGB888 G0

VPBE

GPIO:GPIO[3]

VPBE:

PinMux0:RGB888

PinMux0:LFLDEN

LCD/RGB888, GPIO

RGB888 B0

LCD_FIELD

VPFE CCD, VPBE

GPIO:GPIO[4]

VPBE:

VPFE:

PinMux0:RGB888

PinMux0:CFLDEN

RGB888, GPIO

RGB888 R0

CCD_FIELD

VPBE RGB888,

GPIO:

VPBE:

PinMux0:RGB888

GPIO

GPIO[5:6, 38]

RGB888 G1, B1,

EMIFA, VLYNQ,

GPIO:GPIO[8]

EMIFA:

VLYNQ:

PinMux0:AECS5

PinMux0:VLYNQEN

GPIO

EM_CS5

VLYNQ_CLOCK

EMIFA, VLYNQ,

GPIO:GPIO[9]

EMIFA:

VLYNQ:

PinMux0:AECS4

PinMux0:VLSCREN

GPIO

EM_CS4

VLYNQ_SCRUN

EMIFA, VLYNQ,

GPIO:

EMIFA:

VLYNQ:

PinMux0:AEAW,

PinMux0:VLYNQEN,

GPIO

GPIO[10:17]

EM_A[21:14]

VLYNQ_TXD[0:3],

Pins:DAEAW[4:0]

PinMux0:VLYNQWD[1:0]

VLYNQ_RXD[0:3]

EMIFA, GPIO

GPIO:

EMIFA:

PinMux0:AEAW,

GPIO[18:28]

EM_A[13:3]

Pins:DAEAW[4:0]

(1)

When the secondary function is enabled, to avoid potential contention, ensure that the primary (if not GPIO) and tertiary functions are

disabled.

(2)

When the tertiary function is enabled, to avoid potential contention, ensure that the primary (if not GPIO), secondary, and other tertiary

functions are disabled.

(3)

Pin states are sampled at power on reset and written into the register fields.

Device Configurations

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