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TNETV1647GSTZWT 데이터시트(PDF) 93 Page - Texas Instruments |
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TNETV1647GSTZWT 데이터시트(HTML) 93 Page - Texas Instruments |
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93 / 236 page ![]() Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Manual Timing Reference Point Output Under Test NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data manual timings. 42 Ω 3.5 nH Device Pin (see note) Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Vref Vref = VIL MAX (or VOL MAX) Vref = VIH MIN (or VOH MIN) TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6 Peripheral and Electrical Specifications 6.1 Parameter Information 6.1.1 Parameter Information Device-Specific Information Figure 6-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 6.1.1.1 Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O, Vref = 1.5 V. For 1.8 V I/O, Vref = 0.9 V. Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks. Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 93 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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