TNETV1647GSTZWT datasheet(200/236 Pages) TI1

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SPI_CLK

(Clock Polarity = 0)

SPI_CLK

(Clock Polarity = 1)

SPI_DI

(Input)

SPI_DO

(Output)

MSB IN

DATA

LSB IN

LSB OUT

MSB OUT

DATA

SPI_EN

TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

6.16.2.2 SPI Master Mode Timings (Clock Phase = 1)

Table 6-78. Timing Requirements for SPI Master Mode [Clock Phase = 1](1) (see Figure 6-61)

1.05 V and 1.2 V

NO.

UNIT

MIN

MAX

Setup time, SPI_DI (input) valid before SPI_CLK

tsu(DIV-CLKL)

Clock Polarity = 0

0.5P + 9.4

(output) rising edge

Setup time, SPI_DI (in put) valid before SPI_CLK

tsu(DIV-CLKH)

Clock Polarity = 1

0.5P + 9.4

(output) falling edge

Hold time, SPI_DI (input) valid after SPI_CLK

th(CLKL-DIV)

Clock Polarity = 0

0.5P - 4.5

(output) rising edge

Hold time, SPI_DI (input) valid after SPI_CLK

th(CLKH-DIV)

Clock Polarity = 1

0.5P - 4.5

(output) falling edge

(1)

P = Period of the SPI module clock in nanoseconds (SYSCLK5).

Table 6-79. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode

[Clock Phase = 1] (see Figure 6-61)

1.05 V and 1.2 V

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, SPI_CLK (output) falling edge to SPI_DO

td(CLKL-DOV)

Clock Polarity = 0

-4

(output) transition

Delay time, SPI_CLK (output) rising edge to SPI_DO

td(CLKH-DOV)

Clock Polarity = 1

-4

(output) transition

Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or

td(ENL-CLKH/L)

2P + 0.5C - 2.3

falling edge(1) (2) (3)

Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high

td(CLKL/H-DOHz)

1P - 0.2

impedance

(1)

P = Period of the SPI module clock in nanoseconds (SYSCLK5).

(2)

This delay can be increased under software control by the C2TDELAY register bit field in the SPIDELAY register.

(3)

C = Period of SPI_CLK signal in ns.

Figure 6-61. SPI Master Mode External Timing (Clock Phase = 1)

200

Peripheral and Electrical Specifications

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