TNETV1647GSTZWT datasheet(205/236 Pages) TI1

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TMS320DM6441

www.ti.com

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

6.18.2

ASP Electrical Data/Timing

6.18.2.1

Audio Serial Port (ASP) Timing

Table 6-84. Timing Requirements for ASP(1) (see Figure 6-64)

1.05 V and 1.2 V

NO.

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

38.5 or 2P(2) (3)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

19.25 or P(2) (3) (4)

CLKR int

11.8

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

1.3

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

CLKR int

10.7

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

0.9

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

3.1

CLKX int

12.2

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

1.4

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

P = 1/SYSCLK5 clock frequency in ns. For example, when running parts at DSP frequency of 405 MHz, use P = 14.8 ns.

(3)

Use whichever value is greater.

(4)

The ASP does not require a duty cycle specification, just ensure the minimum pulse duration specification is met.

Peripheral and Electrical Specifications

205

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