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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV1644ZDU6 데이터시트(PDF) 250 Page - Texas Instruments |
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TNETV1644ZDU6 데이터시트(HTML) 250 Page - Texas Instruments |
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250 / 306 page  Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) DX 13(A) 13(A) 2 1 CLKS FSR external CLKR/X (no need to resync) CLKR/X (needs resync) TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0. Figure 6-34. McBSP Timing(B) Table 6-62. Timing Requirements for FSR When GSYNC = 1 (see Figure 6-35) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MIN MAX 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns Figure 6-35. FSR Timing When GSYNC = 1 Peripheral Information and Electrical Specifications 250 Submit Documentation Feedback |
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