TNETV1644ZDU6 datasheet(53/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 2-19. VPFE Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between the VPFE(CCDC) and GPIO.

This pin is CCDC input YI4 and it supports several modes:

YI4(CCD4)/

IPD

In 16-bit CCD Raw mode, it is input CCD4.

D14

C18

I/O/Z

GP[40]

DVDD33

In 16-bit YCbCr mode, it is input Y4.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and

CR4 of the lower 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC) and GPIO.

This pin is CCDC input YI3 and it supports several modes:

YI3(CCD3)/

IPD

In 16-bit CCD Raw mode, it is input CCD3.

B14

A16

I/O/Z

GP[39]

DVDD33

In 16-bit YCbCr mode, it is input Y3.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and

CR3 of the lower 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC) and GPIO.

This pin is CCDC input YI2 and it supports several modes:

YI2(CCD2)/

IPD

In 16-bit CCD Raw mode, it is input CCD2.

C14

B17

I/O/Z

GP[38]

DVDD33

In 16-bit YCbCr mode, it is input Y2.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and

CR2 of the lower 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC) and GPIO.

This pin is CCDC input YI1 and it supports several modes:

YI1(CCD1)/

IPD

In 16-bit CCD Raw mode, it is input CCD1.

B15

B18

I/O/Z

GP[37]

DVDD33

In 16-bit YCbCr mode, it is input Y1.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and

CR1 of the lower 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC) and GPIO.

This pin is CCDC input YI0 and it supports several modes:

YI0(CCD0)/

IPD

In 16-bit CCD Raw mode, it is input CCD0.

C15

B19

I/O/Z

GP[36]

DVDD3

In 16-bit YCbCr mode, it is input Y0.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and

CR0 of the lower 8-bit channel.(4)

C_WE/EM_R/W/

IPD

This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.

D13

C17

I/O/Z

GP[35]

DVDD33

In VPFE mode, it is the CCD Controller write enable input C_WE.

This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.

C_FIELD/EM_A[21]/

IPD

D12

C16

I/O/Z

In VPFE mode, it is CCDC field identification bidirectional signal

GP[34]

DVDD33

C_FIELD.

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