TNETV1644ZDU6 datasheet(278/306 Pages) TI1

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6.18.2

Management Data Input/Output (MDIO) Electrical Data/Timing

MDCLK

MDIO

(input)

MDCLK

MDIO

(output)

6.19 Timers

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 6-90. Timing Requirements for MDIO Input (see Figure 6-48 and Figure 6-49)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tc(MDCLK)

Cycle time, MDCLK

400

tw(MDCLK)

Pulse duration, MDCLK high/low

180

tt(MDCLK)

Transition time, MDCLK

tsu(MDIO-MDCLKH)

Setup time, MDIO data input valid before MDCLK high

th(MDCLKH-MDIO)

Hold time, MDIO data input valid after MDCLK high

Figure 6-48. MDIO Input Timing

Table 6-91. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

(see Figure 6-49)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

td(MDCLKL-MDIO)

Delay time, MDCLK low to MDIO data output valid

100

Figure 6-49. MDIO Output Timing

The DM6437 device has 3 64-bit general-purpose timers which have the following features:

• 64-bit count-up counter

• Timer modes:

–

64-bit general-purpose timer mode (Timer 0 and 1)

–

Dual 32-bit general-purpose timer mode (Timer 0 and 1)

–

Watchdog timer mode (Timer 2)

• 2 possible clock sources:

Peripheral Information and Electrical Specifications

278

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