TNETV1644ZDU6 datasheet(123/306 Pages) TI1

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3.7.3.9 Timer1 Block

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

This block of 2 pins consists of Timer1, HECC, UART1 Data, and GPIO muxed pins. The

PINMUX1.TIM1BK register field selects the pin functions in the Timer1 Block.

Table 3-33 summarizes the 2 pins in the Timer1 Block, the multiplexed function on each pin, and the

PINMUX configurations to select the corresponding function.

Table 3-33. Timer1 Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL

HECC

TIMER1

UART1

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

HECC_RX/

TINP1L/

HECC_RX

TINP1L

URXD1

GP[56]

URXD1/

GP[56]

TIM1BK = 11

TIM1BK = 01

TIM1BK = 10

TIM1BK = 00

HECC_TX/

TOUT1L/

HECC_TX

TOUT1L

UTXD1

GP[55]

UTXD1/

GP[55]

Unlike UART0, UART1 only supports data pins but not flow control pins.

Table 3-34 provides a different view of the Timer1 Block pin muxing, showing the Timer1 Block function

based on PINMUX1.TIM1BK setting. The selection options are also shown pictorially in Figure 3-11.

Table 3-34. Timer1 Block Function Selection

PINMUX1.TIM1BK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (2) (default)

GPIO: GP[56:55]

Timer1

Timer1: TINP1L, TOUT1L

UART1 Data

UART1: URXD1, UTXD1

HECC

HECC: HECC_RX, HECC_TX

In addition, the VDD3P3V_PWDN.TIMER1 field determines the power state of the Timer1 Block pins. The

Timer1 Block pins default to powered down and not operational. To use these pins, user must first

program

VDD3P3V_PWDN.TIMER1

power

the

pins.

For

details

the

VDD3P3V_PWDN.TIMER1 field, see Section 3.2, Power Considerations.

The Timer1 Block features internal pull up resistors, which matches the UART and HECC inactive polarity.

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