TNETV1644ZDU6 datasheet(146/306 Pages) TI1

146 / 306 page

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 3-53. EMIFA/VPSS Sub-Block 1 Configuration Choice D(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

AEM

OTHERS

EMIFA

VPBE

GPIO

OPTION

8-bit EMIFA (NAND)

Cfg Summary

No VENC

22-to-26 GP pins

Pinout Mode 4

VENCSEL = 0

0 = GP[31, 29:14]

0 = EM_A[2:1],

RGBSEL = 0

0 = GP[11:10, 7:5]

EM_CS2

100

CS3SEL = 0,1

1 = EM_CS3

0 = GP[13]

CS4SEL = 0,1

1 = EM_CS4

0 = GP[32]

CS5SEL = 0,1

1 = EM_CS5

0 = GP[33]

1 = VPBECLK,

VPBECKEN = 0,1

can be used by

0 = GP[30]

DAC

8-bit EMIFA (NAND)

Cfg Summary

8-bit VENC

12-to-17 GP pins

Pinout Mode 4

1 = VCLK,

VENCSEL = 1

1 = GP[21:14]

YOUT[7:0]

0 = EM_A[2:1],

EM_CS2

0 = none

0 = GP[11:10, 7:5]

RGBSEL = 0,1

100

1 = EM_A[2:1],

1 = LCD_FIELD

1 = GP[10, 7:5]

EM_CS2

CS3SEL = 0,1,2

1 = EM_CS3

2 = LCD_OE

0 = GP[13]

CS4SEL = 0,1,2

1 = EM_CS4

2 = VSYNC

0 = GP[32]

CS5SEL = 0,1,2

1 = EM_CS5

2 = HSYNC

0 = GP[33]

VPBECKEN = 0,1

1 = VPBECLK

0 = GP[30]

8-bit EMIFA (NAND)

16-to-18-bit

Cfg Summary

2-to-9 GP pins

Pinout Mode 4

VENC

2 = VCLK,

VENCSEL = 2

YOUT[7:0],

COUT[7:0]

0 = EM_A[2:1],

EM_CS2

0 = none

1 = EM_A[2:1],

0 = GP[11:10, 7:5]

1 = LCD_FIELD

EM_CS2

1 = GP[10, 7:5]

100

RGBSEL = 0,1,2,3

2 = R2, B2

2 = EM_A[2:1],

2 = GP[11:10, 7]

3 = R2, B2,

EM_CS2

3 = GP[10, 7]

LCD_FIELD

3 = EM_A[2:1],

EM_CS2

CS3SEL = 0,1,2

1 = EM_CS3

2 = LCD_OE

0 = GP[13]

CS4SEL = 0,1,2

1 = EM_CS4

2 = VSYNC

0 = GP[32]

CS5SEL = 0,1,2

1 = EM_CS5

2 = HSYNC

0 = GP[33]

VPBECKEN = 0,1

1 = VPBECLK

0 = GP[30]

(1)

Italics indicate mandatory setting for a given Minor Configuration option.

146

Device Configurations

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