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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV6446AINZWT 데이터시트(PDF) 151 Page - Texas Instruments |
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TNETV6446AINZWT 데이터시트(HTML) 151 Page - Texas Instruments |
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151 / 227 page  DA[2:0], ATA_CS0, ATA_CS1 tC(A) HDDIR DIOW DD[15:0] (OUT) tC(A) A. tC ≥ one cycle DA[2:0], ATA_CS0, ATA_CS1 HDDIR DIOW DD[15:0] (OUT) tC(A) tC(A) A. tC ≥ one cycle TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 6.11.2.4 ATA/CF HDDIR Timing Figure 6-38 through Figure 6-41 show the behavior of HDDIR for the different types of transfers. Table 6-42. Timing Requirements for HDDIR(1) A-513, -594, NO. UNIT -810 MIN MAX 1 tc Cycle time, ATA_CS[1:0] to HDDIR low E - 3.1 2.1 ns (1) E = ATA clock cycle Figure 6-38. ATA/CF HDDIR Taskfile Write/Single PIO Write Timing Figure 6-39. ATA/CF HDDIR PIO Postwrite Start Timing Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 151 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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