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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV6446AINZWT 데이터시트(PDF) 98 Page - Texas Instruments |
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TNETV6446AINZWT 데이터시트(HTML) 98 Page - Texas Instruments |
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98 / 227 page  TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com 6.4.1 Reset Electrical Data/Timing Table 6-8. Timing Requirements for Reset (see Figure 6-9) A-513, -594, NO. UNIT -810 MIN MAX 1 tw(RST) Width of the RESET pulse 444 ns 2 tsu(BOOT) Setup time, boot configuration bits valid before RESET high 444 ns 3 th(BOOT) Hold time, boot configuration bits valid after RESET high 444 ns Table 6-9. Switching Characteristics Over Recommended Operating Conditions During Reset(1) (see Figure 6-9) A-513, -594, NO. UNIT -810 MIN MAX 26 td(PLL_LOCK) Delay time, PLL1 lock time 2000P ns 4 td(RSTL-DDRZZ) Delay time, RESET low to DDR2 Z Group high impedance 0 2P + 20 ns 5 td(RSTL-DDRLL) Delay time, RESET low to DDR2 Low Group low 0 20 ns 6 td(RSTL-DDRHH) Delay time, RESET low to DDR2 High Group high 0 20 ns 16 td(RSTL-DDRZHZ) Delay time, RESET low to DDR2 Z/High Group high impedance 0 5P + 20 ns 17 td(RSTL-DDRLHL) Delay time, RESET low to DDR2 Low/High Group low 0 20 ns 7 td(RSTL-ZZ) Delay time, RESET low to Z Group high impedance 0 20 ns 8 td(RSTL-LOWL) Delay time, RESET low to Low Group low 0 20 ns 9 td(RSTL-HIGHH) Delay time, RESET low to High Group high 0 20 ns 18 td(RSTL-HIGHLOWH) Delay time, RESET low to High/Low Group high 0 20 ns 19 td(RSTL-LOWHIGHL) Delay time, RESET low to Low/High Group low 0 20 ns 24 td(RSTL-ZIZ) Delay time, RESET low to Z/Invalid Group high impedance 0 20 ns 10 td(RSTH-DDRZV) Delay time, RESET high to DDR2 Z Group valid (2) ns 11 td(RSTH-DDRLV) Delay time, RESET high to DDR2 Low Group valid (2) ns 12 td(RSTH-DDRHV) Delay time, RESET high to DDR2 High Group valid (2) ns 20 td(RSTH-DDRZHV) Delay time, RESET high to DDR2 Z/High Group valid high 4000P ns 21 td(RSTH-DDRLHV) Delay time, RESET high to DDR2 Low/High Group valid high 4000P ns 13 td(RSTH-ZV) Delay time, RESET high to Z Group valid (2) ns 14 td(RSTH-LOWV) Delay time, RESET high to Low Group valid (2) ns 15 td(RSTH-HIGHV) Delay time, RESET high to High Group valid (2) ns 22 td(RSTH-HIGHLOWV) Delay time, RESET high to High/Low Group valid low 5100P ns 23 td(RSTH-LOWHIGHV) Delay time, RESET high to Low/High Group valid high 5100P ns 25 td(RSTH-ZIIV) Delay time, RESET high to Z/Invalid Group invalid 4000P ns (1) P = MXI/CLKIN cycle time, in ns. (2) Following RESET high, this signal group maintains the state the pins(s) achieved while RESET was driven low until the peripheral is enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low and remains in the high-impedance state following RESET high until the DDR2 controller is enabled via the PSC. 98 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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