 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
TNETV6446AINZWT 데이터시트(PDF) 93 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV6446AINZWT 데이터시트(HTML) 93 Page - Texas Instruments |
|
|
93 / 227 page  DSP Subsystem ARM Subsystem VICP SYSCLK1 SYSCLK2 SYSCLK5 SCR EDMA3 VPFE VPBE DACs DDR2 PHY DDR2 VTP DDR2 Mem Ctlr PLLDIV1 (/10) PLLDIV2 (/2) BPDIV PLL Controller 2 PLL Controller 1 PLLDIV3 (/3) PLLDIV5 (/6) PLLDIV2 (/2) PLLDIV1 (/1) SYSCLK3 Bypass Clock UARTs (x3) I2C Timers (x3) ATA/CF EMIF/NAND EMAC VLYNQ MMC/SD SPI GPIO ASP HPI USB 2.0 USB PHY 60 MHz 24 MHz 27 MHz PCLK VPBECLK PLLDIV4 (/4) ARM INTC PWMs (x3) PLLDIV1 (/1) PLLDIV2 (/2) PLLDIV4 (/4) PLLDIV3 (/3) PLLDIV5 (/6) SYSCLK1 SYSCLK2 SYSCLK4 SYSCLK3 SYSCLK5 1 0 Post−DIV PLLM PLL 0 1 BPDIV CLKMODE CLKIN OSCIN PLLEN AUXCLK SYSCLKBP TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Figure 6-6. PLL1 and PLL2 Clock Domain Block Diagram For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-7 and Figure 6-8, respectively. Figure 6-7. PLL1 Structure Block Diagram Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 93 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
