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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV6446AINZWT 데이터시트(PDF) 156 Page - Texas Instruments |
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TNETV6446AINZWT 데이터시트(HTML) 156 Page - Texas Instruments |
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156 / 227 page  MHz 5795454545 . 3 264 35 MHz 27 = ÷ ø ö ç è æ = -ntsc sc f MHz 4332628318 . 4 1017 167 MHz 27 = ÷ ø ö ç è æ = - pal sc f TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com 6.13 Video Processing Sub-System (VPSS) Overview The DM6446 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital LCD panels, HDTV video encoders, etc. Note: The VPSS module is supported with Linux Application Peripheral Interfaces (APIs) commonly used by video application developers. Video for Linux 2 or V4L2 uses APIs commonly used for video capture. The typical use cases of the VPSS Video Front-End (VPFE) have been ported to this Linux API structure. V4L2 supports standard video interfaces such as: BT.656 and Y/C mode. Other modules within the VPSS VPFE for example, the Preview Engine, H3A, and Histogram are not currently supported within the software APIs. The VPSS Back-End (VPBE) uses FBDev/DirectFB as the APIs. Certain functionalities within the VPBE have not been implemented in the FBDev/DirectFB APIs. For modes/functions not implemented in software, it is the user's responsibility to modify the software drivers/APIs. The VPSS register memory mapping is shown in Table 6-46. Table 6-46. VPSS Register Descriptions HEX ADDRESS REGISTER ACRONYM DESCRIPTION RANGE 0x01C7 3400 PID Peripheral Revision and Class Information 0x01C7 3404 PCR VPSS Control Register 0x01C7 3408 - Reserved 0x01C7 3508 SDR_REG_EXP SDRAM Non Real-Time Read Request Expand 0x01C7 350C - - Reserved 0x01C7 3FFF To ensure NTSC- and PAL-compliant output video, the stability of the input clock source is very important. TI recommends a 27-MHz, 50-ppm crystal. Ceramic oscillators are not recommended. The NTSC/PAL color sub-carrier frequency is derived from the 27-MHz clock. Therefore, if the 27-MHz clock drifts, then the color sub-carrier frequency will drift as well. Assuming no 27-MHz frequency drift, the color sub-carrier frequency is generated as follows: To ensure the color sub-carrier frequency will not drift out of spec, the user must follow the crystal requirements discussed in Section 6.5.1, Clock Input Option 1 – Crystal. Alternatively, if the VPBE input clock is sourced from the VPBECLK or VPFE clock inputs, these clocks must have a frequency stability of ±50 ppm to ensure the NTSC and PAL compliant output video. 156 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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