 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
TNETV6446AINZWT 데이터시트(PDF) 144 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV6446AINZWT 데이터시트(HTML) 144 Page - Texas Instruments |
|
|
144 / 227 page  TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com 6.11.2.3 ATA/CF Ultra DMA Timing Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing(1) (2) (see Figure 6-28 through Figure 6-37) A-513, -594, NO. MODE UNIT -810 MIN MAX 28 f(SYSCLK5) Operating frequency, SYSCLK5 0-4 25 MHz 0 240 ns 1 160 ns 1 t2CYCTYP Typical sustained average two cycle time 2 120 ns 3 90 ns 4 60 ns 2 tCYC Cycle time, Strobe edge to Strobe edge 0-4 (UDMASTB + 1)P ns Two cycle time, rising to rising edge or falling to 3 t2CYC 0-4 2(UDMASTB + 1)P ns falling edge 0 15 ns 1 10 ns 4 tDS Data setup, data valid before STROBE edge 2-3 7 ns 4 5 ns 5 tDH Data hold, data valid after STROBE edge 0-4 5 ns 0 70 ns 1 48 ns Data valid INPUT setup time, data valid before 2 31 ns STROBE 6 tDVS 3 20 ns 4 6.7 ns Data valid OUTPUT setup time, data valid before 0-4 (UDMASTB)P - 3.1 ns STROBE Data valid INPUT hold time, data valid after 0-4 6.2 ns STROBE 7 tDVH Data valid OUTPUT hold time, data valid after 0-4 1P - 2 ns STROBE CRC word valid setup time at host, CRC valid 10 tCVS 0-4 (UDMASTB)P ns before DMACK negation CRC word valid hold time at sender, CRC valid 11 tCVH 0-4 2P ns after DMACK negation Time from STROBE output released-to-driving 12 tZFS 0-4 0 ns until the first transition of critical timing 0 70 ns 1 48 ns Time from data output released-to-driving until 13 tDZFS 2 31 ns the first transition of critical timing 3 20 ns 4 6.7 ns (1) P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 594 MHz, use P = 10.1 ns. For example, when running the DSP CPU at 810 MHz, use P = 7.4 ns. (2) UDMASTB equals the value programmed in the UDMSTBxP bit field in the UDMASTB register. UDMATRP equals the value programmed in the UDMTRPxP bit field in the UDMATRP register. TENV equals the value programmed in the UDMATNVxP bit field in the UDMATENV register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21). 144 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
