DocID025003 Rev 1

19/29

A6727

Application details

To place the poles and zeroes of the compensation network, the following suggestions may

be followed:

a)

to 5 k

Ω):

Equation 7

b)

c)

d)

e)

check that compensation network gain is lower than open loop EA gain;

f)

estimate phase margin obtained (it should be greater than 45°) and repeat,

modifying parameters, if necessary.

9.3

Layout guidelines

The A6727 provides control functions and high-current integrated drivers to implement high-

current step-down DC-DC converters. In this kind of application, a good layout is very

important.

When placing components, the power section is the first priority because the length of each

connection and loop have to be reduced as minimum as possible. To minimize noise and

voltage spikes (EMI and losses), power connections (highlighted in Figure 10) must be part

of a power plane and realized by wide and thick copper traces: loop must be minimized. The

critical components, such as the power MOSFETs, must be very close one to the other. The

use of multi-layer printed circuit board is recommended.

placed close to the power section in order to eliminate the stray inductance generated by

the copper traces. Low ESR and ESL capacitors are preferred, MLCC should be connected

near the HS drain.

Use a proper number of vias when power traces have to move between different planes on

the PCB in order to reduce both parasitic resistance and inductance. Moreover, the same

R

F

R

FB

----------

F

0dB

F

LC

------------

ΔV

OSC

V

IN

-------------------

⋅

=

C

F

1

π R

F

F

LC

⋅⋅

-----------------------------

=

C

P

C

F

2

π R

F

C

F

F

ESR

1

–

⋅⋅

⋅

----------------------------------------------------------

=

R

S

R

FB

F

SW

2F

⋅

LC

------------------

1

–

---------------------------

=

C

S

1

π R

S

F

SW

⋅⋅

-------------------------------

=