L6985F datasheet(5/65 Pages) STMICROELECTRONICS

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L6985F

Pin settings

2.1

Pin connection

Figure 2. Pin connection (top view)

2.2

Pin description

Table 1. Pin description

No.

Description

1RST

The RST open collector output is driven low when the output voltage is out of regulation. The RST

is released after an adjustable time DELAY once the output voltage is over the active delay

threshold.

2VCC

Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the

embedded analog circuitry.

SS/INH

An open collector stage can disable the device clamping this pin to GND (INH mode). An internal

current generator (4

A typ.) charges the external capacitor to implement the soft-start.

SYNCH/

ISKP

The pin features Master / Slave synchronization in LNM (see Section 6.5 on page 45) and skip

current level selection in LCM (see Section 4.5.2 on page 24).

5FSW

A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the switching frequency.

Pinstrapping is active only before the soft-start phase to minimize the IC consumption.

6MLF

A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the low noise mode/low

consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start

phase to minimize the IC consumption.

COMP

Output of the error amplifier. The designed compensation network is connected at this pin.

8DELAY

An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the

RST o. c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like

a Power Good.

Inverting input of the error amplifier

SGND

Signal GND

PGND

Power GND

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