L6751 datasheet(28/59 Pages) STMICROELECTRONICS

부품명	L6751

상세설명	Digitally controlled dual PWM for Intel VR12 and AMD SVI

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Device configuration and pinstrapping tables

L6751

28/59

Doc ID 023992 Rev 1

Transition threshold specified as delta with respect to previous step (DPM23 is wrt DPM12).

GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two different

pinstrappings DPM1-3 and DPM4-6. See Table 12 for details.

Transition between 1Phase and 2Phase operation is set to 12 A but disabled in PS00h.

Dynamic phase management disabled, IC always working at maximum possible number of phases

except from when in >PS00h when transitioning between 1Phase and 2Phase at 12 A.

Table 12.

GDC threshold definition(1)

GDC1

GDC0

Threshold [A](2)

GDC OFF

GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two different

pinstrappings DPM1-3 and DPM4-6. See Table 11 for details.

N is the number of phase programmed for the multi-phase section.

N17A

⋅

N13A

⋅

N9A

⋅

L6751 데이터시트(PDF) 28 Page - STMicroelectronics