SPC56EL70L3 datasheet(8/128 Pages) STMICROELECTRONICS

부품명	SPC56EL70L3

상세설명	4 KB instruction cache with error detection code

PDF	128 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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8 / 128 page

Introduction

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

8/128

DocID023953 Rev 5

1.3

Device comparison

Table 1. SPC56XL70/SPC56X64 device summary

Feature

SPC56EL64

SPC56EL70

SPC564L64

SPC564L70

CPU

Type

2 × e200z4

(in lock-step or

decoupled

operation)

2 × e200z4

(in lock-step or

decoupled

operation)

1 × e200z4

Architecture

Harvard

Execution

speed

0–120 MHz (+2% FM)

DMIPS intrinsic

performance

>240 MIPS

SIMD

(DSP + FPU)

Yes

MMU

16 entry

Instruction set

PPC

Yes

Instruction set

VLE

Yes

Instruction

cache

4 KB, EDC

MPU-16

regions

Yes, replicated module

Semaphore unit

(SEMA4)

Yes

Buses

Core bus

AHB, 32-bit address, 64-bit data

Internal

periphery bus

32-bit address, 32-bit data

Crossbar

Master × slave

ports

Lock Step Mode: 4 × 3

Decoupled Parallel Mode: 6 × 3

4 x 3

Memory

Code/data flash

1.5 MB, ECC,

RWW

2 MB, ECC, RWW 1.5 MB, ECC, RWW

2 MB, ECC, RWW

Static RAM

(SRAM)

160 KB, ECC

192 KB, ECC

160 KB, ECC

192 KB, ECC

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