SPC563M64L7 datasheet(25/48 Pages) STMICROELECTRONICS

25 / 48 page

SPC563Mxx

Device overview

Doc ID 13850 Rev 6

25/48

drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU core is

via the crossbar switch. The SIU provides the following features:

●

System configuration

–

MCU reset configuration via external pins

–

Pad configuration control for each pad

–

Pad configuration control for virtual I/O via DSPI serialization

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System reset monitoring and generation

–

Power-on reset support

–

Reset status register provides last reset source to software

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Glitch detection on reset input

–

Software controlled reset assertion

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External interrupt

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11 interrupt requests

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Rising or falling edge event detection

–

Programmable digital filter for glitch rejection

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Critical Interrupt request

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Non-Maskable Interrupt request

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GPIO

–

GPIO function on 80 I/O pins

–

Virtual GPIO on 64 I/O pins via DSPI serialization (requires external

deserialization device)

–

Dedicated input and output registers for setting each GPIO and Virtual GPIO pin

●

Internal multiplexing

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Allows serial and parallel chaining of DSPIs

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Allows flexible selection of eQADC trigger inputs

–

Allows selection of interrupt requests between external pins and DSPI

3.3.8

ECSM

The error correction status module provides status information regarding platform memory

errors reported by error-correcting codes.

3.3.9

Flash

Devices in the SPC563Mxx family provide up to 1.5 MB of programmable, non-volatile, flash

memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.

The flash module includes a Fetch Accelerator, that optimizes the performance of the flash

array to match the CPU architecture and provides single cycle random access to the flash

@ 80 MHz. The flash module interfaces the system bus to a dedicated flash memory array

controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit

data bus width at the system bus port, and a 128-bit read data interface to flash memory.

The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which

prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits

allow no-wait responses. Normal flash array accesses are registered and are forwarded to

the system bus on the following cycle, incurring three wait-states. Prefetch operations may

be automatically controlled, and are restricted to instruction fetch.

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