SPC563M64L7 datasheet(5/48 Pages) STMICROELECTRONICS

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SPC563Mxx

Introduction

Doc ID 13850 Rev 6

5/48

Introduction

The SPC563Mxx is a family of system-on-chip devices that are built on Power Architecture®

technology and:

●

Are 100% user-mode compatible with the classic Power Architecture instruction set

●

Contain enhancements that improve the architecture’s fit in embedded applications

●

Include additional instruction support for digital signal processing (DSP)

●

Integrate technologies, such as an enhanced time processor unit, enhanced queued

analog-to-digital converter, Controller Area Network, and an enhanced modular input-

output system, that are important for today’s lower-end powertrain applications

This document describes the features of the SPC563Mxx and highlights important electrical

and physical characteristics of the device.

1.1

Document overview

This document provides an overview and describes the features of the device series of

microcontroller units (MCUs). For functional characteristics, refer to the device reference

manual. For electrical specifications and package mechanical drawings, refer to the device

data sheet. Pin assignments can be found in both the reference manual and data sheet.

1.2

Description

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that

contain all the features of the SPC563Mxx family and many new features coupled with high

performance 90 nm CMOS technology to provide substantial reduction of cost per feature

and significant performance improvement.

The advanced and cost-efficient host processor core of this automotive controller family is

built on Power Architecture technology. This family contains enhancements that improve the

architecture’s fit in embedded applications, includes additional instruction support for digital

signal processing (DSP), integrates technologies — such as an enhanced time processor

unit, enhanced queued analog-to-digital converter, Controller Area Network, and an

enhanced modular input-output system — that are important for today’s lower-end

powertrain applications.

The device has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM

and up to 1.5 MB of internal flash memory. The device also has an external bus interface

(EBI) for ‘calibration’. This external bus interface has been designed to support most of the

standard memories used with the SPC564Axx and SPC563Mxx families.

SPC563Mxx is part of a family of devices that contain many new features coupled with high

performance 90 nm CMOS technology to provide substantial reduction of cost per feature

and significant performance improvement.

The host processor core of the SPC563Mxx complies with the Power Architecture Book E. It

is 100% user mode compatible (with floating point library) with the classic Power

Architecture instruction set. The Book E architecture has enhancements that improve the

Power Architecture’s fit in embedded applications. In addition to the classic Power

Architecture instruction set, this core also has additional instruction support for digital signal

processing (DSP).

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