| 전자부품 데이터시트 검색엔진 |
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SRC0 데이터시트(PDF) 14 Page - STMicroelectronics |
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SRC0 데이터시트(HTML) 14 Page - STMicroelectronics |
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14 / 48 page ![]() Waveforms SRC0 14/48 DocID026008 Rev 2 4 Waveforms Figure 7. Successful power-up on SRC0 (PB released prior to tON_BLANK expiration) 1. PB detection on falling and rising edges. 2. Internal pull-down resistor 300 k is connected to PS HOLD input during power-up. 3. EN signal is high even after PB release, because processor sets PSHOLD signal high before PB is released. PSHOLD ignored internal pull-down resistor connected to PSHOLD input VCC undervoltage detection ignored PB (1) PSHOLD (2) EN (3) RST Push-button pressed and PB connected to GND tDEBOUNCE tREC processor sets PSHOLD PB released prior to t ON_BLANK expiration PSHOLD state detected as high EN remains asserted tON_BLANK AM00247v3 INT signal is held high during power-up (i.e. until PB release in this case). V CC is considered VCC > VTH+. Note: |
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