ST7DALIF2 datasheet(109/171 Pages) STMICROELECTRONICS

109 / 171 page

ST7DALIF2

Serial peripheral interface (SPI)

109/171

17.6

Interrupts

Note:

The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

17.7

17.7.1

Control register (SPICR)

Read/Write

Reset Value: 0000 xxxx (0xh)

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or

Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register)

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode,

SS=0 (see Master mode fault (MODF) on page 105). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable.

This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0]

bits to set the baud rate. Refer to Table 48: SPI master mode SCK frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note:

This bit has no effect in slave mode.

Table 47.

Interrupt control bits

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of Transfer Event

SPIF

SPIE

Yes

Master Mode Fault Event

MODF

Yes

Overrun Error

OVR

Yes

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

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