ST7DALIF2 datasheet(110/171 Pages) STMICROELECTRONICS

110 / 171 page

Serial peripheral interface (SPI)

ST7DALIF2

110/171

Bit 4 = MSTR Master Mode.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode,

SS=0 (see Master mode fault (MODF) on page 105).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output and the

functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL Clock Polarity.

This bit is set and cleared by software. This bit determines the idle state of the serial Clock.

The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note:

The slave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used with the SPR2 bit, they select the baud

rate of the SPI serial clock SCK output by the SPI in master mode.

Note:

These 2 bits have no effect in slave mode.

17.7.2

Control/status register (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only).

This bit is set by hardware when a transfer has been completed. An interrupt is generated if

Table 48.

SPI master mode SCK frequency

Serial clock

SPR2

SPR1

SPR0

fCPU/4

fCPU/8

fCPU/16

fCPU/32

fCPU/64

fCPU/128

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

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